<div><p>We are now looking for a Senior Circuit Timing Engineer!</p><br/><p><b>What you'll be doing:</b></p><ul><li>Participate in ground breaking processor design in deep submicron technologies.</li><li>Work as part of a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions.</li><li>Drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal).</li><li>Validate timing of custom circuit designs using STA tools including Nanotime, PrimeTime, Tempus and various SPICE simulation tools.</li><li>Collaborate with cross-functional teams to improve the power, performance, area and reliability of NVIDIA's next generation products through custom circuit solutions and detailed transistor-level analysis.</li><li>Develop timing models and methodology for innovative and unique custom macro designs.</li><li>Transistor-level circuit design and timing, schematic entry, and layout delivery.</li><li>Integrate AI/ML techniques directly into the design process and methodology.</li><li>Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, as well as timing ECO implementation.</li></ul><p><b>What we need to see:</b></p><ul><li>BSEE/MS preferred in Electrical, Computer Engineering or equivalent experience.</li><li>6+ years of digital circuit design experience for Masters and 8+ years for Bachelors.</li><li>Excellent understanding of deep submicron process issues and digital circuit design techniques is required.</li><li>Expertise and in-depth knowledge of industry standard STA tools such as Nanotime, Primetime, Tempus, and other timing analysis tools.</li><li>Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure is required.</li><li>Proven experience in timing constraints generation and management.</li><li>Hands on experience in design and analysis of low power circuits (power gating, decaps, multi-vt, etc..) is a plus.</li><li>Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise.</li><li>Solid understanding of extracted timing models and the usage of .libs in Primetime.</li><li>Knowledge of process variation effect modeling and experience in design convergence in multi GHz deep submicron technology.</li></ul><p> </p><p><b>Ways to stand out from the crowd:</b></p><ul><li>Proven ownership and hands-on experience across the entire silicon design flow, from micro-architecture and RTL design to back-end execution, including Custom/Semi-Custom Circuit Design, Synthesis, Auto Place and Route, STA, and PVerf.</li><li>Proven capability in Post-Silicon characterization and debug, ensuring designs meet performance targets in hardware.</li><li>Track record of independently driving and delivering complex features from conception through tape-out and validation.</li><li>Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs.</li></ul><p></p><p></p>Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.<div><div><div><div><div><div><div><p></p><p>You will also be eligible for equity and benefits.</p><p></p></div></div></div></div></div></div></div>Applications for this job will be accepted at least until October 15, 2026.<p></p><p>This posting is for an existing vacancy. </p><p>NVIDIA uses AI tools in its recruiting processes.</p><p></p></div>